Electronic System Level Design | Faculty of Technical Sciences

Subject: Electronic System Level Design (17.EM458)

Native organizations units: Department of Power, Electronic and Telecommunication Engineering

General information:

Category	Scientific-professional
Scientific or art field	Electronics
ECTS	6

Acquiring knowledge about the system level design techniques of embedded systems. Learning how to use standard languages, techniques and methodologies, as well as tools for the successful design of embeded system at the system level.

- ability to develop a system level model of the embedded system using some of the standard System Level languages - ability to profile and optimize system level performance based on the design goals - ability to verify developed embedded system at the system level

Methodology of System-Level design. Models of computation used at system level: finite state machines (FSMs), dataflow, process networks. System-Level design languages: MATLAB, SystemC, SpecC. System-Level modeling: transaction-level modeling (TLM) for communication, processor and RTOS modeling. Specification, profiling and analysis of HW/SW systems. Codesign of hardware and software. System-Level design methodologies and tools for: partitioning, scheduling and communication synthesis. High Level synthesis. System-Level design of low power systems. Verification at the System-Level: verification based on simulation, verification based on formal methods, coverification of hardware and software.

Lectures. Computer labs. Consultations.

Authors	Title	Year	Publisher	Language
D. D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner	Embedded System Design: Modeling, Synthesis, Verification	2009	Springer Verlag	English
M. Fujita, I. Ghosh, M. Prasad	Verification Techniques for System Level Design	2008	Morgan Kaufmann	English
B. Bailey, G. Martin, A. Piziali	ESL Design and Verification - A Prescription for Electronic System Level Methodology	2007	Morgan Kaufmann	English