Subject: Hardware Description Languages (17 - EM302)

Basic Information

Scientific or art field:Electronics
Native organizations units

Course native organizational units not found!
Course specification

Course is active from 29.08.2017..

Course which have preconditioned courses Hardware Description Languages

Course idMandatoryMandatory
Discrete Signals and SystemsYesYes
Architectures of microcomputer systemsYesYes
Design of Complex Digital SystemsYesYes
Functional Hardware VerificationYesYes
Fault Tolerant DesignYesYes
Teaching students in using contemporary hardware description languages for digital systems modeling, as well as learning how to use software tools for simulation, synthesis and implementation of developed hardware models. Teaching students how to write simulation, as well as synthesizable models of standard combinational and sequential digital networks. Learning how to design more complex digital systems, using hierarchical and modular design methodologies.
- ability to develop simulation, as well as synthesis HDL models for all standard types of combinatorial and sequential networks - ability of developing HDL models of more complex digital systems, using hierarchical and modular design methodologies - ability to develop basic testbenches that can be used for functional verification of developed HDL models - ability to perform all required design implementation steps (synthesis, implementation, bitstream configuration) in the process of FPGA implementation of developed HDL models
Introduction into hardware description languages. Hierarchical and modular design methodologies. Introduction to VHDL language. Scalar data types and operations in VHDL. Concurrent statements in VHDL. Sequential statements in VHDL. Composite data types and operations in VHDL. Basic modeling constructs. Subprograms. Packages and generic constants. Generate statements. Files and Input/Output in VHDL. Introduction to hardware verification. Introduction to automatic hardware synthesis. Available technologies for hardware implementation of HDL models. FPGA and ASIC technology.
Lectures; Auditory Practice; Computer Practice; Laboratory Practice; Consultations.
Peter AshendenThe Designers Guide to VHDL2008Morgan KaufmannEnglish
Course activity Pre-examination ObligationsNumber of points
Computer excersise defenceYesYes50.00
Written part of the exam - tasks and theoryNoYes50.00
Name and surnameForm of classes
Missing picture!

Struharik Rastislav
Full Professor

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Vranjković Vuk
Associate Professor

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Bortnik Dušan

Laboratory classes
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Pilipović Nebojša

Laboratory classes
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Bratić Stojanka
Teaching Associate

Laboratory classes