IMPLEMENTACIJA PROTOKOLA ZA KOHERENTNOST KEŠ MEMORIJE
Ključne reči:
Multiprocessor Systems, Cache coherence, MESI, FPGA
Apstrakt
U ovom radu prikazana je implementacija MESI protokola za koherentnost keš memorije, kao i ostatka multiprocesorskog sistema sastavljenog od RISC-V procesora i dva nivoa keš memorije. Pomoću bihevijalne simulacije testirano je ponašanje sistema u situaciji kada se iz drugog nivoa keš memorije izbacuje blok koji su modifikovala dva jezgra.
Reference
[1] W. Stallings, “Computer Organization and Architecture: Designing for Performance”, 9th ed. Boston, MA: Pearson, 2013.
[2] D. Culler, J. P. Singh, and A. Gupta, “Parallel Computer Architecture: A Hardware/Software Approach”, San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 1998.
[3] T. Suh, “Integration and evaluation of cache coherence protocols for multiprocessor socs”, 2006.
[4] V. Nagarajan, D. J. Sorin, M. D. Hill, and D. A. Wood, “ A Primer on Memory Consistency and Cache Coherence”, 2nd ed. Morgan & Claypool Publishers, 2020
[5] R. H. Katz et al., “Implementing a cache consistency protocol”, ACM SIGARCH Computer Architecture News, vol. 13, no. 3, pp. 276-283, 1985.
[2] D. Culler, J. P. Singh, and A. Gupta, “Parallel Computer Architecture: A Hardware/Software Approach”, San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 1998.
[3] T. Suh, “Integration and evaluation of cache coherence protocols for multiprocessor socs”, 2006.
[4] V. Nagarajan, D. J. Sorin, M. D. Hill, and D. A. Wood, “ A Primer on Memory Consistency and Cache Coherence”, 2nd ed. Morgan & Claypool Publishers, 2020
[5] R. H. Katz et al., “Implementing a cache consistency protocol”, ACM SIGARCH Computer Architecture News, vol. 13, no. 3, pp. 276-283, 1985.
Objavljeno
2023-12-06
Sekcija
Elektrotehničko i računarsko inženjerstvo
