PROJEKTOVANJE TAKTOVANIH CMOS KOMPARATORA
Ključne reči:
Komparatori, kašnjenje, CMOS tehnologija, projektovanje analognih integrisanih kola.
Apstrakt
U ovom radu je opisano projektovanje taktovanih komparatora pomoću tri često korišćene topologije. Prikazani su najvažniji parametri koji određuju kvalitet kola. Rezultati simulacija kola na nivou lejauta sa ekstrahovanim parazitima su upoređeni sa drugim radovima.
Reference
[1] D. Johns, K. Martin, Analog integrated circuit design, USA, 1997.
[2] B. Goll, H. Zimmermann, Comparators in Nanometer CMOS Technology, Austria, 2015.
[3] G. M. Yin, F. Op’t Eynde, and W. Sansen, A High-speed CMOS Comparator with 8-b Resolution, IEEE Journal of Solid-State Circuits. VOL. 27 , no. 2, 1992.
[4] Behzad Razavi, The StrongARM Latch, IEEE Journal of Solid-State Circuits, 25 June 2015.
[5] S. Bindra, C. E. Lokin, A. Annema, B. Nauta, A 30fJ/comparison Dynamic Bias comparator, Integrated Circuit Design, 2017.
[6] A. Sathishkumar, S. Saravanan, Analysis and Design of Low Power High Speed Dynamic Latch Comparator using CMOS Process, International Journal of Scientific & Engineering Research, vol. 5, pp. 2229-5518, May 2014.
[7] B. S. Patro, S. Biswas, I. Roy, B. Vandana , 1 GHz High Sensitivity Differential Current Comparator for High Speed ADC, Journal of Digital Integrated Circuits in Electrical Devices, vol. 2, no. 1, 2017.
[8] Khorami and M. Sharifkhani, A Low-Power High-Speed Comparator for Precise Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, pp. 2038–2049, 2018.
[9] N. Ghaziani, S. Radfar, Y. Bastan, P. Amiri and M. H. Maghami, A Low-Power Low-Voltage Dynamic Comparator in 180nm CMOS Technology, 2020 28th Iranian Conference on Electrical Engineering (ICEE), 2020.
[2] B. Goll, H. Zimmermann, Comparators in Nanometer CMOS Technology, Austria, 2015.
[3] G. M. Yin, F. Op’t Eynde, and W. Sansen, A High-speed CMOS Comparator with 8-b Resolution, IEEE Journal of Solid-State Circuits. VOL. 27 , no. 2, 1992.
[4] Behzad Razavi, The StrongARM Latch, IEEE Journal of Solid-State Circuits, 25 June 2015.
[5] S. Bindra, C. E. Lokin, A. Annema, B. Nauta, A 30fJ/comparison Dynamic Bias comparator, Integrated Circuit Design, 2017.
[6] A. Sathishkumar, S. Saravanan, Analysis and Design of Low Power High Speed Dynamic Latch Comparator using CMOS Process, International Journal of Scientific & Engineering Research, vol. 5, pp. 2229-5518, May 2014.
[7] B. S. Patro, S. Biswas, I. Roy, B. Vandana , 1 GHz High Sensitivity Differential Current Comparator for High Speed ADC, Journal of Digital Integrated Circuits in Electrical Devices, vol. 2, no. 1, 2017.
[8] Khorami and M. Sharifkhani, A Low-Power High-Speed Comparator for Precise Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, pp. 2038–2049, 2018.
[9] N. Ghaziani, S. Radfar, Y. Bastan, P. Amiri and M. H. Maghami, A Low-Power Low-Voltage Dynamic Comparator in 180nm CMOS Technology, 2020 28th Iranian Conference on Electrical Engineering (ICEE), 2020.
Objavljeno
2022-11-02
Sekcija
Elektrotehničko i računarsko inženjerstvo
