VERIFIKACIJA REKONFIGURABILNE ARHITEKTURE ZA HARDVERSKU AKCELERACIJU PREDIKTIVNIH MODELA MAŠINSKOG UČENJA
Ključne reči:
funkcionalna verifikacija, mašinsko učenje, hardverska akceleracija, univerzalna verifikaciona metodologija (UVM), SystemVerilog
Apstrakt
U ovom radu je predstavljena funkcionalna verifikacija rekonfigurabilne arhitekture za hardversku akceleraciju prediktivnih modela mašinskog učenja - Reconfigurable Machine Learning Classifier (RMLC).
Reference
[1] V. Vranjković, “Rekonfigurabilne arhitekture za hardversku akceleraciju prediktivnih modela mašinskog učenja“, Autorski reprint, 139., 2015.
[2] L. Rokach, O. Maimon, “Series in Machine Perception and Artificial Intelligence – Vol. 69, Data Mining with Decision Trees Theory and Applications”, Worlds Scientific Publishing Co. Pte. Ltd, 2008.
[3] V. Sze, Y. Chen, J. Emer, A. Suleiman, Z. Zhang, “Hardware for Machine Learning: Challenges and Opportunities”, Massachusetts Institute of Technology Cambridge, MA 02139, Oktobar 2017.
[4] G. Lacey, G. Taylor, S. Areibi, “Deep Learning on FPGAs: Past, Present, and Future”, University of Guelph 50 Stone Rd E Guelph, Ontario, Februar 2016.
[5] B. Wile, John C. Goss, W. Roesner, “Comprehensive Functional Verification: The Complete Industry Cycle”, Library of Congress Cataloging-in-Publications Data, ISBN: 0-12-78183-7, 2005.
[6] “Universal Verification Methodology (UVM) 1.2 User’s Guide”, Accellera Systems Initiative (Accellera). Accellera Systems Initiative, 8698 Elk Grove Bldv Suite 1, #114, Elk Grove, CA 95624, USA, 2011 – 2015.
[7] Mozhikunnath, R., Garg, R. “Cracking Digital VLSI Verification Interview Interview Success”, 2016.
[2] L. Rokach, O. Maimon, “Series in Machine Perception and Artificial Intelligence – Vol. 69, Data Mining with Decision Trees Theory and Applications”, Worlds Scientific Publishing Co. Pte. Ltd, 2008.
[3] V. Sze, Y. Chen, J. Emer, A. Suleiman, Z. Zhang, “Hardware for Machine Learning: Challenges and Opportunities”, Massachusetts Institute of Technology Cambridge, MA 02139, Oktobar 2017.
[4] G. Lacey, G. Taylor, S. Areibi, “Deep Learning on FPGAs: Past, Present, and Future”, University of Guelph 50 Stone Rd E Guelph, Ontario, Februar 2016.
[5] B. Wile, John C. Goss, W. Roesner, “Comprehensive Functional Verification: The Complete Industry Cycle”, Library of Congress Cataloging-in-Publications Data, ISBN: 0-12-78183-7, 2005.
[6] “Universal Verification Methodology (UVM) 1.2 User’s Guide”, Accellera Systems Initiative (Accellera). Accellera Systems Initiative, 8698 Elk Grove Bldv Suite 1, #114, Elk Grove, CA 95624, USA, 2011 – 2015.
[7] Mozhikunnath, R., Garg, R. “Cracking Digital VLSI Verification Interview Interview Success”, 2016.
Objavljeno
2018-12-19
Sekcija
Elektrotehničko i računarsko inženjerstvo
